1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a device for sensing a data in a multi-bit memory cell.
2. Background of the Related Art
In general, semiconductor memories come in two varieties: volatile and nonvolatile. In a volatile memory, information recorded therein can be erased and new information can then be stored in the same memory. Included in this memory category is the random access memory (RAM). In a non-volatile memory, on the other hand, once information is recorded, it can be retained permanently in the memory.
A read only memory (ROM) is a non-volatile memory that cannot be reprogrammed once information is written to it. On the other hand, an erasable programmable read only memory (EPROM) and an electronically erasable programable read only memory (EEPROM) are non-volatile memories that have the capacity to be erased and reprogrammed with new information that will remain until the device is erased again. The programming operations of the EPROM and the EEPROM are the same, but the erasing operations are different. The EPROM uses an ultraviolet light to erase information stored thereon, while the EEPROM use electricity to erase information stored thereon.
As information industries develop, large sized memories become necessary. The Dynamic RAM (DRAM) is one of the most widely used mass storage medias to meet such a requirement. A drawback of the DRAM, however, is that a relatively large storage capacitor is required, which necessitates reflash operations in fixed intervals. Consequently, the EEPROM has been studied as a possible replacement for the DRAM, since the EEPROM requires no reflash operations.
The EEPROM memory, however, can only record data of either a "1" or a "0" on one memory cell. Hence, the packing density of the EEPROM memory corresponds to the number of memory cells in a one to one fashion. Therefore, the largest drawback to the EEPROM is that cost-per-bit of the memory is too expensive.
In order to solve this problem, studies on multibit-per-cell EEPROMs have been recently proposed. The multibit-per-cell EEPROMs store data of two bits or more in one memory cell, thereby enhancing the density of data on the same chip area without reducing the size of the memory cell. For the multibit-per-cell memory, multi-threshold voltage levels should be programmed on the respective memory cells. For instance, in order to store data of more than two bits for every cell, the respective cells must be programmed in 2.sup.2, that is, four, threshold levels. Here, the four threshold levels correspond to logic states 00, 01, 10, and 11, respectively. To increase the number of bits that can be stored in every cell, more threshold levels need to be programmed for each cell by precisely adjusting the respective threshold levels, thus reducing a distribution width of the threshold voltage levels.
A related art device for sensing multi-level programmed data will be described with reference to the attached drawings. FIG. 1a illustrates a related art circuit for sensing data from a multi-bit cell, and FIG. 1b illustrates a table for detecting a data storage state in a memory cell by a sensing operation of the related art circuit in FIG 1a. In the related art circuit for sensing a data from a multi-bit cell, the multi-bit cell is sensed with reference to a voltage.
Referring to FIG. 1a, the related art circuit for sensing data from a multi-bit cell is provided with a memory cell 1 for storage of data, a first PMOS transistor PM1 having a source terminal in contact with a drain terminal of the memory cell 1 at a first contact node CN1 and a gate terminal connected to the source terminal, and a reference voltage generating unit 5 for generating a plurality of reference voltages. First, second, and third comparing units 2, 3, and 4 compare a voltage from the memory cell to first, second, and third reference voltages Vref1, Vref2, and Vref3 generated in a reference voltage generating unit 5 respectively. A decoding logic unit 6 receives signals X1, X2, and X3 from the first, second, and third comparing units 2, 3, and 4 and decodes a data storage state of the memory cell 1. The drain terminal of the first PMOS transistor PM1 is supplied with a source voltage V.sub.DD.
The memory cell 1 is selected when a Vin signal is provided thereto. Then, the data stored in the memory cell is provided to the first, second, and third comparing units 2, 3, and 4 through the first contact node CN1, and compared to the first, second, and third reference voltages Vref1, Vref2, and Vref3 to provide the outputs X1, X2, and X3. The decoding logic unit 6 receives the outputs X1, X2, and X3 and converts and outputs the data from the memory cell in a binary form.
A process for sensing the data storage state of the related art memory cell 1 when Vref1&lt;Vref2&lt;Vref3 will be described with reference to FIG. 1b. It is assumed that the multi-bit memory cell has been programmed on four levels 00, 01, 10, and 11 of threshold voltages. First, when a voltage lower than first reference voltage the Vref1 is provided to the first, second, and third comparing units 2, 3, and 4 through the first contact node CN1, each of the outputs X1, X2, and X3 from the first, second, and third comparing units 2, 3, and 4 are at a low level L. On reception of the output signals X1, X2, and X3, the decoding logic unit 6 outputs a 0 through both the A terminal and the B terminal. These outputs indicate that the data stored in the memory cell 1 is at a (00)th level of the four levels of a 00, 01, 10, and 11.
When a voltage higher than the first reference voltage Vref1, but lower than the second reference voltage Vref2 is provided to the first, second, and the third comparing units 2, 3, and 4 through the first contact node CN1, a high signal H is provided from the output terminal X1 on the first comparing unit 2, and low signals L are provided both from the second and third comparing units 3 and 4. Upon reception of the output signals, the decoding logic unit 6 provides 0, 1 from the A terminal and the B terminal, respectively. This output indicates that the data stored in the memory cell 1 is programmed to (01)th level of the four levels.
Next, when a voltage higher than the second reference voltage Vref2, but lower than the third reference voltage Vref3 is provided to the first, second, and third comparing units 2, 3, and 4 through the first contact node CN1, high signals H are provided from the output terminals X1 and X2 on the first and second comparing units 2, and 3, and a low signal L is provided from the output terminal X3 on the third comparing unit 4. Upon reception of the output signals, the decoding logic unit 6 provides 1, 0 from the A terminal and the B terminal, respectively, indicating that the data stored in the memory cell 1 is programmed to (10)th level of the four levels.
Finally, when a voltage higher than the third reference voltage Vref3 is provided to the first, second, and third comparing units 2, 3, and 4 through the first contact node CN1, high signals H are provided from the output terminals X1, X2, and X3 on the first, second, and third comparing units 2, 3, and 4. Upon reception of the output signals, the decoding logic unit 6 provides 1, 1 from the A terminal and the B terminal respectively, indicating that the data stored in the memory cell 1 is programmed to (11)th level of the four levels.
Referring to FIGS. 2a and 2b, the related art circuit for sensing data from a multi-bit memory cell compares a voltage distribution at the first contact node CN1 (i.e., a sensing node) coming from the threshold voltages of the memory cell to the generated reference voltages. That is, .DELTA.V.sub.M =.DELTA.V.sub.M ' (where .DELTA.V.sub.M =a gap between the threshold voltages and .DELTA.V.sub.M '=a gap between sensing node voltages). When the threshold voltage distribution of the memory cell is used as the sensing node voltage distribution as it is, it may be difficult to set the reference voltages precisely if the gaps between the threshold voltages are narrow. The threshold voltage is dependent on various external factors such as fabrication process, temperature, trap charge in a tunnel oxide film in the memory, and so on.
As described above, the related art circuit for sensing a data from a multi-bit memory cell has various problems. For example, a plurality of reference voltages or a plurality of reference currents are used for sensing a programmed or erased state of a multi-bit memory cell with a plurality of threshold voltage levels. Since a threshold voltage distribution inevitably occurs because of a variety of external parameters, such as variation of process characteristics, precision of the reference voltages, and temperature variation, the sensing reliability drops because the threshold voltage distribution is used as it is. Additionally, since gaps between threshold voltages become narrower as a number of bits increases the widths of the threshold voltages increase relatively, and the sensing reliability drops.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.